摘要： 在SM9加密等算法中经常使用大数乘法，为了解决大数乘法中关键电路延迟过高、能耗过大的问题，设计了一种基于流水线的可重构1 024位乘法器。使用64位乘法单元和128位先行进位加法单元，分20个周期流水产生最终结果，缓解了传统乘法器中加法部分的延时，实现电路复用，有效减小能耗。在SMIC 0.18 μm工艺库下，关键电路延迟2.5 ns，电路面积7.03 mm2 ，能耗576 mW。

中图分类号：TN402 文献标志码：A DOI: 10.16157/j.issn.0258-7998.234199
中文引用格式： 苏成，夏宏. 一种高效能可重构1 024位大数乘法器的设计[J]. 电子技术应用，2024，50(3)：31-35.
英文引用格式： Su Cheng，Xia Hong. Design of an efficient and reconfigurable 1 024 bit large numbers multiplier[J]. Application of Electronic Technique，2024，50(3)：31-35.

Design of an efficient and reconfigurable 1 024 bit large numbers multiplier

Abstract： Large number multiplication is often used in algorithms such as SM9 encryption. In order to solve the problem of high delay and energy consumption in key circuits in large number multiplication, a reconfigurable 1 024 bit multiplier based on pipeline was designed. By using 64 bit multiplication units and 128 bit carry ahead addition units, the final result is generated in 20 cycles, alleviating the delay of the addition part in traditional multipliers, achieving circuit multiplexing, and effectively reducing energy consumption. In the SMIC 0.18 μm process library, the critical circuit has a delay of 2.5 ns, a circuit area of 7.03 mm2, and an energy consumption of 576 mW.

Key words : large number multiplication；pipeline；Wallace tree；reconfigurable