摘要： 随着芯片设计规模和复杂度越来越大，传统的芯片EDA（Electronic Design Automation）验证方法在子系统和SoC（System on Chip）全芯片级别越来越受限于仿真速度限制。如何高效收敛RTL（Register Transfer Level）设计，确保及时高质量交付，成为芯片研发领域急需解决的重要问题。介绍了一种自研的利用分布式计算方法来加速大型芯片仿真效率的DVA（Distributed Verification Acceleration）系统架构和实现。

中图分类号：TN402 文献标志码：A DOI: 10.16157/j.issn.0258-7998.233800
中文引用格式： 王锋，张栗榕，王磊. 一种基于分布式计算的芯片仿真加速设计[J]. 电子技术应用，2024，50(1)：31-34.
英文引用格式： Wang Feng，Zhang Lirong，Wang Lei. Design of SoC/SIP simulation acceleration based on distributed computing[J]. Application of Electronic Technique，2024，50(1)：31-34.

Design of SoC/SIP simulation acceleration based on distributed computing

Abstract： With the continuous growth of IC design scale and complexity, traditional EDA verification is more and more restricted especially for sub-system and SoC full chip level simulation efficiency. To efficiently and effectively find and debug RTL problems and ensure the IC delivery quality and time to market has become the critical path for IC development. This article introduces a platform (DVA) based on distributed computing method to accelerate large scale IC verification. The DVA platform based on UVM, adopts native Linux socket components as underlying layer for communication.

Key words : IC development；EDA；distributed computing；simulation acceleration