摘要： 提出了一种SoC芯片时钟方案，并设计了两种版图方案。针对模块中产生电磁干扰的原因进行分析，通过判断信号间隔离度仿真结果，可提前识别版图方案中是否存在信号间干扰风险，进而恶化SoC芯片输出模拟信号质量。根据信号间隔离度仿真结果指导版图设计，并给出优化版图方法，改善了信号间隔离度性能。测试结果表明，版图设计两种方案的仿真结果与实测结果吻合，验证了仿真结果的准确性、可参考性。

中图分类号：TN74
文献标志码：A
DOI: 10.16157/j.issn.0258-7998.223049
中文引用格式： 马世娟，肖永平，倪晓东. 射频模块中晶振对电磁兼容影响研究[J]. 电子技术应用，2023，49(2)：102-105.
英文引用格式： Ma Shijuan，Xiao Yongping，Ni Xiaodong. Research of the influence of crystal oscillator on EMC in RF module[J]. Application of Electronic Technique，2023，49(2)：102-105.

Research of the influence of crystal oscillator on EMC in RF module

Abstract： This paper proposes a SoC chip clock scheme and designs two layout schemes. By analyzing the causes of electromagnetic interference and judging the simulation results of the isolation degree between signals, the risk of inter-signal interference in the layout scheme can be identified in advance, which will deteriorate the output analog signal quality of SoC chip. In this paper, the simulation results of the isolation degree between signals are used to guide the layout design, and the optimization layout method is given to improve the performance of the isolation degree between signals. The test results show that the simulation results of the two layout design schemes are consistent with the actual results, which verifies the accuracy and reference of the simulation results.

Key words : EMC；EMI；digital-analog hybrid；isolation