摘要： 随着嵌入式系统小型化和模拟数字/数字模拟转换器(ADC/DAC)性能需求的日益增长，如何在减小系统体积和功耗的前提下，提高ADC/DAC信号传输的可靠性，增加功能可配置性和信号处理可重构性，成为一大难题。为此，设计了一款基于FPGA的系统级封装(SiP)原型验证平台，该SiP基于ADC+SoC+DAC架构，片上系统(SoC)内部以PowerPC470为处理器，集成了多种通用外设接口和可重构算法单元。

中图分类号： TN401
文献标识码： A
DOI：10.16157/j.issn.0258-7998.211700
中文引用格式： 杨楚玮，张梅娟，侯庆庆. 基于FPGA的SiP原型验证平台设计[J].电子技术应用，2022，48(1)：84-88，93.
英文引用格式： Yang Chuwei，Zhang Meijuan，Hou Qingqing. The designation of SiP prototype verification platform based on FPGA[J]. Application of Electronic Technique，2022，48(1)：84-88，93.

The designation of SiP prototype verification platform based on FPGA

Abstract： With the growing demand of embedded system miniaturization and the performance of analog-to-digital/digital-to-analog converter(ADC/DAC), it is a big problem how to improve the reliability of ADC/DAC signal transmission, increase the function configurability and signal processing reconfigurability on the premise of reducing system volume and power consumption. Thus, this paper designs a system in package(SiP) prototype verification platform based on FPGA, used to verify the feasibility and reliability of this SiP architecture.

Key words : prototype verification；reconfigurable algorithm；bare machines IP；FPGA