摘要： 针对DDR3系统设计对时序要求的特殊性，对某一SiP(System in Package)中DDR3封装和基板设计进行时序仿真和优化，通过仿真指导设计，提高SiP产品DDR3的设计成功率，减少设计周期。通过ANSYS SIwave软件提取信号S参数，再经过Cadence SystemSI软件搭建拓扑进行时序仿真分析，利用信号完整性相关理论，讨论信号时序与波形的关系，结合版图分析，给出实际的优化方案，并经过仿真迭代验证，最终使所设计的DDR3满足JEDEC协议中的时序要求。

中图分类号： TN405.97
文献标识码： A
DOI：10.16157/j.issn.0258-7998.211370
中文引用格式： 王梦雅，曾燕萍，张景辉，等. 基于SiP封装的DDR3时序仿真分析与优化[J].电子技术应用，2021，47(10)：42-47.
英文引用格式： Wang Mengya，Zeng Yanping，Zhang Jinghui，et al. Timing simulation analysis and optimization of DDR3 based on SiP package[J]. Application of Electronic Technique，2021，47(10)：42-47.

Timing simulation analysis and optimization of DDR3 based on SiP package

Abstract： Aiming at the timing requirements of DDR3 system, timing simulation and optimization were carried out for DDR3 package and substrate design in a SiP(System in Package). Through simulation guidance design, the design success rate of DDR3 in SiP product was improved and the design cycle was reduced. The signal scattering parameters were extracted by ANSYS SIwave software, and then the topology construction and timing simulation analysis was carried out through Cadence SystemSI software. The relationship between signal timing and waveform was discussed based on the theory of signal integrity. The actual optimization scheme was given by combining with layout analysis. Finally, the designed DDR3 system could meet the timing requirements of JEDEC protocol through simulation iteration verification.

Key words : DDR3；SiP(system in package)；timing simulation；high density interconnection；signal integrity