摘要： 介绍了基于HVCMOS工艺的低成本、高集成度、强驱动性能功率集成电路(Power IC，PIC)H桥的设计实现。建立的金属互连线评估模型可在设计早期对H桥物理版图方案进行优差性判断，不依赖设计后仿真,从而提高设计效率。H桥不同互连线设计方案的比较结果表明，多插指阵列器件互连线(M2及以上层金属)与器件本体的金属层M1垂直、梯形状互连结构，能够提高互连线沿电流流向的有效长宽比，减小寄生电阻。

中图分类号： TN492
文献标识码： A
DOI：10.16157/j.issn.0258-7998.201078
中文引用格式： 李芳，焦继业，马彩彩. 基于 HVCMOS工艺的H桥驱动电路版图设计[J].电子技术应用，2021，47(6)：35-39.
英文引用格式： Li Fang，Jiao Jiye，Ma Caicai. H-bridge driver circuit layout design based on HVCMOS technology[J]. Application of Electronic Technique，2021，47(6)：35-39.

H-bridge driver circuit layout design based on HVCMOS technology

Abstract： The design and realization of a H-bridge which is power integrated circuit(Power IC, PIC) and based on the HVCMOS process with low cost, high integration and strong driving performance is introduced. The established metal interconnection evaluation model can judge the H-bridge physical layout in the early stage of the design and does not rely on post-design simulation, thereby improving design efficiency.The comparison result of different interconnection design of H-bridge shows that the interconnection of multi-finger array device(M2 layer and above metal) is perpendicular to the metal layer M1 of the device and ladder-shaped structure can improve the effective aspect ratio of the interconnection along the current flow direction, thus reduce parasitic resistance.

Key words : HVCMOS；H-bridge；high integration；low on-resistance