飞思卡尔16位MCU MC9S12XD, S12XB & S12XA系列数据手册

详情,请下载:飞思卡尔16位MC9S12XDP512V2数据手册.pdf

 

  The MC9S12XD family will retain the low cost, power consumption, EMC and code-size efficiency
advantages currently enjoyed by users of Freescale's existing 16-Bit MC9S12 MCU Family.

 

  Based around an enhanced S12 core, the MC9S12XD family will deliver 2 to 5 times the performance of
a 25-MHz S12 whilst retaining a high degree of pin and code compatibility with the S12.

 

  The MC9S12XD family introduces the performance boosting XGATE module. Using enhanced DMA
functionality, this parallel processing module offloads the CPU by providing high-speed data processing and transfer between peripheral modules, RAM, Flash EEPROM and I/O ports. Providing up to 80 MIPS of performance additional to the CPU, the XGATE can access all peripherals, Flash EEPROM and the RAM block.

 

  The MC9S12XD family is composed of standard on-chip peripherals including up to 512 Kbytes of Flash
EEPROM, 32 Kbytes of RAM, 4 Kbytes of EEPROM, six asynchronous serial communications interfaces
(SCI), three serial peripheral interfaces (SPI), an 8-channel IC/OC enhanced capture timer, an 8-channel,10-bit analog-to-digital converter, a 16-channel, 10-bit analog-to-digital converter, an 8-channel pulse-width modulator (PWM), five CAN 2.0 A, B software compatible modules (MSCAN12), two
inter-IC bus blocks, and a periodic interrupt timer. The MC9S12XD family has full 16-bit data paths
throughout.

通知公告
编辑观点
理事会
参考资料
版权声明

凡《网络安全与数据治理》(原《信息技术与网络安全》)录用的文章,如作者没有关于汇编权、翻译权、印刷权及电子版的复制权、信息网络传播权与发行权等版权的特殊声明,即视作该文章署名作者同意将该文章的汇编权、翻译权、印刷权及电子版的复制权、信息网络传播权与发行权授予本刊,本刊有权授权本刊合作数据库、合作媒体等合作伙伴使用。同时,本刊支付的稿酬已包含上述使用的费用,特此声明。

《网络安全与数据治理》(原《信息技术与网络安全》)编辑部